&nbs= p; &= nbsp; &nbs= p; =
60-265 <=
/span>COMP=
UTER
SYSTEM ARCHITECTURE I: DIGITAL DESIGN
Solution for Midterm #1=
Question: 1 (a)=
(12
Marks)
Use
Boolean algebra to prove that
X.Y + X’.Y=
.Z +
X.Y.Z + Y.Z’.W’ + Z’.W + Y.Z’.W <=
span
style=3D'font-size:12.0pt;font-family:"Arial","sans-serif";mso-bidi-font-we=
ight:
bold'>=3D Y + Z’.W
State the Identities u=
sed,
if any, at each step.
Hint: Some of the identities, which may be used are:<= o:p>
1 + A =3D 1; A.1
=3D A; A + A’ =3D=
1; A
+ A’.B =3D A + B
Solution:
X.Y + X’.Y.Z + X.Y.Z +
Y.Z’.W’ + Z’.W + Y.Z’.W
=3D Y (X + X’Z + XZ
+Z’W’ + Z’W) + Z’W
=3D Y (X + Z + XZ +Z’)=
+
Z’W
By using A + A’B =3D A + B, A + A’ =3D 1, A.1 =3D A
=3D Y (X + XZ +1) + Z’=
W
By using A + A’ =3D 1
=3D Y + Z’W =3D RHS
By using 1 + A =3D 1, A.1 =3D A
Question: 1 (b) (4 Marks)
Given a
function: F1=
(X, Y,
Z, W) =3D Y + Z’.W.
Implement the
function by using NAND gates only.
Solution:
F1(X, Y, Z, W) =
=3D Y +
Z’W
F1(X, Y, Z, W) =
=3D (Y +
Z’W)’’ =3D (Y’. (Z’W)’)’
![3D1B](3D"IS09MidTerm1_Sol_files/image001.jpg")
Question: 1 (c)=
(4Marks)
For the followi=
ng
network (Fig. 1), find the Boolean expressions for ANY TWO of W, X, Y and Z=
in
terms of A, B, C and D.
=
![](3D"IS09MidTerm1_Sol_files/image003.jpg")
&=
nbsp; &nbs=
p; &=
nbsp; FIG.1
H=
int:
Find the output functions by going from left to right and by determining the
output of each gate.
<= o:p>
Solution:
W =3D A + B. (C+ D)
X =3D B’. (C + D) +
B.C’.D’
Y =3D C’.D’ + C.=
D
Z =3D D’
<= o:p>
Question: 2 (a)=
(12
Marks)
A
Logic Function F2(A, B, C, D) has the followi=
ng
Prime Implicants:
Obtain its Karnaugh Map.
Hint: For each =
Prime
Implicant go through the following two steps:
S=
tep 1:
Select the rows and columns, corresponding to the literals in the Prime
Implicant.
S=
tep 2:
Put 1’s in the cells lying at the inter-section of the selected rows =
and
columns.
Which
of the Prime Implicants of F2<=
/sub>(A,
B, C, D) are
Essential?
Solution:
|
K-MAP |
CD |
||||
|
AB |
|
00 |
01 |
11 |
10 |
|
00 |
0 |
1 |
1 |
0 |
|
|
01 |
1 |
1 |
1 |
0 |
|
|
11 |
1 |
0 |
0 |
0 |
|
|
10 |
1 |
1 |
0 |
0 |
Essential P.I.: A’.D <= o:p>
Question: 2 (b)=
(8
Marks)
Obtain the Karnaugh Map for
=
F3(A, B, C, D) =
=3D ∑ m(1, 5,=
6, 7,
11, 12, 13, 15).
From the Karnaugh Map, find the simplified
expression for F3(A, B, C, D) in
‘Product Of Sum (POS)’ form.
Solution:
|
K-MAP |
CD |
||||
|
AB |
|
00 |
01 |
11 |
10 |
|
00 |
0 |
1 |
0 |
0 |
|
|
01 |
0 |
1 |
1 |
1 |
|
|
11 |
1 |
1 |
1 |
0 |
|
|
10 |
0 |
0 |
1 |
0 |
F3 (A, B, C, D) =
=3D (A + C
+ D). (A + B + C’). (A’ + B + C). (A’ + C’+ D)
Question: 3 (a)=
(8
Marks)
Write
the Truth table for a Full Adder.
Solution:
|
A |
B |
Cin |
S |
Cout |
|
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
1 |
0 |
|
0 |
1 |
0 |
1 |
0 |
|
0 |
1 |
1 |
0 |
1 |
|
1 |
0 |
0 |
1 |
0 |
|
1 |
0 |
1 |
0 |
1 |
|
1 |
1 |
0 |
0 |
1 |
|
1 |
1 |
1 |
1 |
1 |
Question: 3 (b)=
(12
Marks)
Write
the expressions for the Sum and Carry-output in terms of the three inputs of
the Full Adder so that the Full Adder can be implemented by using two XOR
gates, two AND gates and one OR gate.
Draw
the schematic diagram of the Full Adder by using two XOR gates, two AND gat=
es
and one OR gate.
Solution:
Cout =3D A’=
.B.Cin
+ A.B’.Cin + A.B. Cin’ + A.B. C
=3D (A’.B + A.B&=
#8217;)
Cin + A.B
![](3D"IS09MidTerm1_Sol_files/image004.gif")
=3D
(A B)=
. Cin
+ A.B
S =3D A’.B’. C
=3D (A’.B’
+ A.B). Cin + (A’.B + A.B’). Cin’
![](3D"IS09MidTerm1_Sol_files/image005.gif")
Let P =3D A B =3D A=
217;.B +
A.B’
P’ =3D (A’.B +
A.B’)’ =3D (A + B’). (A’ + B) =3D A.A’ + A.B +
A’.B’ + B.B’ =3D A.B + A’.B’
![](3D"IS09MidTerm1_Sol_files/image006.gif")
![](3D"IS09MidTerm1_Sol_files/image007.gif")
S =3D P’. Cin + P. Cin̵=
7; =3D
P C
![3D3B](3D"IS09MidTerm1_Sol_files/image009.jpg")
Question: 3 (c)=
(10
Marks)
Use
three Full Adders and one Half Adder to draw the schematic diagram of a 4-b=
it
Adder.
Solution:
![3D3C](3D"IS09MidTerm1_Sol_files/image011.jpg")
Question: 4 (a)=
(10
Marks)
F4(A, B, C, D) =3D Σ ( m(=
1, 3,
4, 11, 12, 15).
Use a 8-to-1 MUX, along with an Inverter,=
to
obtain an implementation.
H=
int: A
few of the inputs of the MUX may be connected to 0.
<= o:p>
Solution:
Y =3D A’.B’.C’.I0 + A’.B’.C.I1 + A’.B.C’= ;I2 + A’.B.C.I3 + A.B’.C’.I4 + A.B’.C.I5 + A.B.C’= .I6 + A.B.C.I7<= o:p>
F4 =3D
A’.B’.C’.D + A’.B’.C.D +
A’.B.C’.D’ + A.B’.C.D + A.B.C’.D’ + A.B=
.C.D
Comparing
Y with F4
D =3D I0 =3D
I1 =3D I5 =3D I7
D’
=3D I2 =3D I6
0 =3D I3 =3D
I4
![3D4A-1](3D"IS09MidTerm1_Sol_files/image013.jpg")
Question: 4 (b)=
(10
Marks)
Use two 3-to-8 Active Low Decoders and an
inverter to obtain an Active Low 4-to-16 Decoder. Assume that each of the t=
wo
3-to-8 Active Low Decoders has an Active Low Enable input.
Solution:
![3D4B](3D"IS09MidTerm1_Sol_files/image015.jpg")
Question: 4 (c)=
(10
Marks)
Use the Active Low 4-to-16 Decoder, along
with two gates to obtain an
implementation for the following two functions:
(i)&=
nbsp; F4(A=
, B,
C, D) =3D Σ ( m(1, 3, 4, 11, 12, 15)
(ii)=
F5(A=
, B,
C, D) =3D Σ ( m(1, 3, 4, 5, 9, 10, 11, 12, 13, 14, 15).
For implementing each of the two function=
s F4(A,
B, C, D) and F5(A, B, C, D), choose a gate with as small a value of fan-in as possible.
Solution:
![3D4C](3D"IS09MidTerm1_Sol_files/image017.jpg")
* &n=
bsp; * &=
nbsp; * &=
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nbsp; * &=
nbsp; * &=
nbsp; * &=
nbsp; * &=
nbsp; *